1. Field of the Invention
The present invention relates to methods of forming gate electrodes in semiconductor devices. More particularly, the present invention relates to forming SiGe gate electrodes using a thin nucleation layer.
2. Description of the Related Art
As features on semiconductor devices, such as integrated circuit chips, continue to decrease in size thinner gate dielectric films are required. For example, a 90 nm gate node may require a gate dielectric thickness of about 15 Angstroms. Even with these thin gate dielectric films, the overlying polysilicon gate electrode layer will likely continue to be relatively thicker. The gate electrode layers need a certain minimum thickness to have adequate conductivity. Thick electrode layers used in conjunction with thin dielectrics present several problems.
Typically a photoresist layer is applied on top of the electrode layer and patterned using photolithographic processes. The patterned photoresist conventionally has a thickness proportional to the thickness of the gate electrode material being etched. A relatively thick photoresist layer has been conventionally used with plasma etching to prevent areas of the wafer covered by the photoresist from exposure by the etching chemicals as they etch the uncovered portion of the gate electrode layer. A certain thickness of photoresist has been required with conventional processes in the past to last through the plasma etch step used to pattern the electrode material.
The high aspect ratios resulting from the patterning of thick gate electrode materials to very small dimensions presents major challenges for the photolithography process.
Thick photoresist layers limit the optical resolution obtainable on the wafer. Subsequent etching of the thick electrode material without breaking through the thin gate dielectric will be very difficult since variations in thickness and etch rate of the thick electrode material across the wafer result in the gate dielectric material being exposed sooner in some regions than in other regions. This, in turn, can result in the etch penetrating through the thin dielectric material rather than stopping short of break through. Penetration can result in unacceptable attack of the underlying source/drain silicon regions, resulting in device reliability and yield problems. Moreover, variation in the etching characteristics of the electrode material and variations in the thickness of the electrode material will result in across the wafer and wafer to wafer variability which may translate into variations of the gate edge slope. In addition, lateral etching problems presented by the thick electrode material may result in problems in critical dimension control.
Accordingly, it is desirable to produce a gate electrode using thin photoresist layers and very short and controllable etch sequences.
To achieve the foregoing, the present invention provides an unconventional method of forming gate electrodes in semiconductor devices. In one aspect, the invention provides a SiGe gate electrode formed using a thin silicon nucleation layer. A dielectric layer is formed on a semiconductor wafer and the thin silicon nucleation layer deposited on top of the dielectric layer and patterned to form the base of a gate electrode. A SiGe (silicon germanium) conducting film is deposited on the gate electrode nucleation layer. The ratio of germanium to silicon in the gaseous source mixture for the silicon and germanium conducting film is selected so that the SiGe conducting film deposits on the nucleation layer but fails to deposit on the dielectric. The method enables the selective deposition of a gate electrode with the use of very thin photoresist layers to pattern a thin base layer. The deposited silicon nucleation layer is also thin and thus requires only short, controllable etch sequences.
In one aspect, the invention provides a method of forming a gate electrode on a semiconductor device. A dielectric layer is formed on the semiconductor wafer. A thin silicon layer is deposited on the dielectric layer. In one aspect the silicon layer is void free and has a thickness in the range from about 50 Angstroms to 2000 Angstroms. The silicon layer is patterned and etched to form a gate electrode nucleation layer. A silicon germanium conducting film is deposited on the nucleation layer. The silicon germanium source gas mixture is selected so that the film deposits on the gate electrode nucleation layer but fails to deposit on the dielectric layer. In another aspect, the deposited silicon layer is a monolayer.
In another aspect a metal layer is deposited on the deposited silicon germanium conducting film. The metal layer is annealed to form a low resistance germanide silicide contact.
In yet another aspect, a gaseous mixture comprising the germane and silane further comprises dopants for doping the silicon layer. The ratio of germane to at least one of silane and dichlorosilane (SiH2Cl2) is in the range from about 0.025 to 1.00.